1. Field of the Invention
This invention relates to a microprocessor incorporating a cache memory and particularly relates to a microprocessor incorporating a cache memory unit characterized by its cache replacement control when the incorporated cache memory fails to hit.
2. Description of the Related Art
Recent microprocessors tend to incorporate a cache memory for speedy memory access. The performance of such microprocessors mainly depends on the capacity and block size of their incorporating cache memory. The larger the cache memory capacity is, the higher the data hit ratio becomes with improving the microprocessor performance. Microprocessors, however, require a number of control circuits inside and the incorporated cache memory capacity cannot be more than a few kilobytes due to limitation imposed by chip size. This results in a low hit ratio at present.
The block size is the quantity of data to be replaced at a time upon a miss at the cache memory. Since one block is contiguously disposed on the memory, the hit ratio of the cache memory becomes higher for a larger block size in case of contiguous programs and data. For non-contiguous data, however, the hit ratio becomes lower even if the block size is large; a large block size may deteriorate the performance because many bus cycles are needed for a single cache memory replacement.
In a typical microprocessor with an incorporated cache memory, an instruction code is output from a cache memory in a cache unit and sent to an instruction execution unit via a data bus. Then, the instruction execution unit decodes the instruction code and executes the processing directed by the instruction code. If the instruction involves a memory access, then the applicable memory address is sent to the cache unit via an address bus. The cache unit, upon receipt of the address, indexes the cache memory contained therein via the address. If the desired data is located in the cache memory, the applicable data in the cache memory is immediately sent to the instruction execution unit via the data bus.
If the desired data is not located (miss) in the cache memory, the cache control circuit in the cache unit outputs a cache replacement request signal so that the main storage is accessed via an external address terminal and an external data terminal for cache memory replacement. In this case, the cache memory outputs a miss address to the external address terminal and the data read out of the main storage is registered to the internal cache memory via the external data terminal. The cache replacement request signal is kept active until completion of a series of cache replacement procedures, during which the instruction execution unit cannot proceed to the next instruction execution.
In a conventional microprocessor incorporating a cache memory as described above, the number of bus cycles required for cache replacement is fixed. Therefore, when many bus cycles are needed for cache replacement, access of non-contiguous data involves long waiting time for cache replacement completion (time from the transfer of data which caused the miss until access to the cache memory after replacement completion) in case of a miss at the cache memory, which may result in lower processing performance.